1. Field of the Invention
The present invention relates to a memory cell array.
2. Description of Related Art
Currently, further miniaturization of an electrical element is desired as a device is getting smaller and its density is increasing. As an example of such case, there has been known a switching element which can perform a switching operation by applying a voltage between two conductive bodies facing each other across a microscopic space (nanogap).
Specifically, for example, there has been developed a switching element which is composed of stable material of oxide silicon and gold, manufactured by a simple manufacturing method of oblique vapor deposition, and capable of repeating switching operation stably (for example, see Japanese Patent Application Laid-Open No. 2005-79335).
There has also been developed a switching element which can be arranged at a high density and its integration becomes easy by aligning two conductive bodies facing each other across a nanogap in vertical direction (for example, see Japanese Patent Application Laid-Open No. 2008-243986).
In order to apply such switching element (hereinafter referred to as “nanogap element”) including the nanogap to a high-density memory, it is necessary to relate a “low resistance state” and “high resistance state” which corresponds to “ON” and “OFF” respectively to “zero (0)” and “one (1)” of the memory, and arranging nanogap elements in an array to construct a memory cell array.
Conventionally, as a memory cell array, there has been known a Dynamic Random Access Memory (DRAM) memory cell array (for example, see Japanese Patent Application Laid-Open No. 2000-269358).
A memory cell provided in the DRAM memory cell array includes, for example, a memory cell containing a metal-oxide semiconductor (MOS) transistor and a capacitor as shown in FIG. 6.
As a memory cell array which uses a nanogap element as a memory element, for example, the memory cell array which is obtained by replacing a capacitor of a DRAM memory cell with the nanogap element and driven by a method similar to that for the DRAM memory can be considered.
However, since the nanogap element needs high voltage for writing the data, only by replacing the capacitor of the DRAM memory with the nanogap element and driving it by a method similar to that for the DRAM memory cell array, there is a problem that an area of a high withstand voltage type (high voltage type) transistor occupies a great part of a layout of the memory cell array and its peripheral circuits, and it would penalize a miniaturization of the memory cell array.
In addition, only by replacing the capacitor of the DRAM memory with the nanogap element and driving it by a method similar to that for the DRAM memory cell array, it is impossible to separate high voltage system circuits from low voltage system circuits. As a result, there is a problem that designing or manufacturing the memory cell array or its peripheral circuits becomes complicated and cumbersome.